Engineer / Senior Engineer – IC Verification
- Department: IC Design & Development
- Reporting To: Manager – IC Design & Development
- Location: Singapore
- Position Summary:
- Perform ASIC Verification
- Develop & maintain verification environment for module and SOC level using UVM methodology
- Create and debug test cases ; IP verification
- Write and review verification plan
- Use assertion based verification to verify module or SOC level
- Perform code coverage analysis on module and SOC level
- Any reasonable task assigned by management and deemed to be within the individual’s capabilities to ensure smooth running of the business.
- As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.
Knowledge & Skill Requirements
- Degree / Master in Electrical / Electronic Engineering
- 2 years or above experience in the area of digital IC verification. Candidates with more years of experience may be considered for Senior Engineer position.
- Working experience from design to tape-out are essential
- Experience in system Verilog and UVM verification methodology
- Experience in using EDA tools from Cadence, Synopsys
- Knowledge and working experience in one or more of the following is a plus:
- Digital and mixed-signal design
- Microprocessor / Graphics processor products
- Knowledge in connectivity technology such as USB, WIFI, Bluetooth, RFID, NFC, GPS, UART, SPI and I2C
- Embedded programming using C language
Working conditions are normal for an office environment with willingness to work in a flexible schedule.
We provide a professional, fun and exciting work environment where innovation and creativity thrive!
Interested applicants email your CV along with a cover letter in Word or pdf format to email@example.com